The present claimed invention relates to the field of semiconductor devices. More specifically, the present claimed invention relates to semiconductor device isolating structures.
Shallow groove isolation, sometimes referred to as xe2x80x9cshallow trench isolationxe2x80x9d (STI), is a semiconductor fabrication technique used in the formation of semiconductor device isolating structures. As an example, STI can be used to form a field oxide region separating two semiconductor devices. More specifically, STI is sometimes used as an alternative to conventional semiconductor device isolating methods such as, for example, local oxidation of silicon (LOCOS).
Referring now to Prior Art FIGS. 1A-1C, side-sectional views illustrating steps used in a prior art STI process are shown. As shown in Prior Art FIG. 1A, a substrate 100 has an oxide 102 and nitride 104 stack formed thereon. The oxide 102 and nitride 104 stack are used to mask underlying semiconductor substrate 100 during subsequent STI process steps.
As shown in Prior Art FIG. 1B, using conventional masking and photolithography steps, a typical STI process forms an opening 106 extending through the oxide 102 and nitride 104 stack. The step is commonly referred to as a exsitu etch and is accomplished using a CF4 and O2 etch chemistry. Opening 106 extends to the top surface of semiconductor substrate 100. This is done outside the trench etch tool.
Referring next to FIG. 1C, this is after resist removal and formation of opening 106. The first step in the STI process is the breakthrough step which is accomplished normally using CF4 etch chemistry. In this etch step, native oxide is removed and the wafer is now ready for the normal trench etch process. In a conventional STI process, a plasma etch or other type of dry etch is then used to etch an opening or xe2x80x9ctrenchxe2x80x9d 108 into semiconductor substrate 100. In a conventional STI process, a common etch chemistry comprised of chlorine, hydrogen bromide, helium, and oxygen (Cl2/HBr/He/O2) is used to etch trench 108 into semiconductor substrate 100. As shown in the cross-sectional view of trench 108 in Prior Art FIG. 1C, a conventional STI process results in the formation of a trench 108 having bottom corners, typically shown as 110a and 110b, which are not rounded. Thus, a trench formed by a conventional STI process does not have a substantially rounded bottom corners.
As is known in the art, prior art trench 108 is typically subsequently filled with dielectric material. However, due to the non-rounded nature of corners 110a and 110b, significant disadvantages are realized. Such sharp corners 110a and 110b reduce semiconductor device isolation effectiveness and device reliability. Specifically, the sharp corners 110a and 110b of prior art trench 108 generate stress during thermal processing. This stress causes dislocations, and may eventually result in reduced leakage protection.
Thus, a need exists for a shallow trench isolation method which produces a trench which does not have sharp bottom corners therein. A further need exists for a shallow trench isolation method which produces a trench having rounded bottom corners.
The present invention provides a shallow trench isolation method which produces a trench which does not have sharp bottom corners therein. The present invention further provides a shallow trench isolation method which produces a trench having rounded bottom corners.
Specifically, in one embodiment, the present invention performs a breakthrough etch to remove a native oxide layer disposed over a region of a semiconductor substrate. In so doing, a region of the semiconductor substrate is exposed. Next, the present embodiment etches a trench into the semiconductor substrate using a first etching environment. In this embodiment, the first etching environment is comprised of chlorine, hydrogen bromide, helium, and oxygen. The present embodiment then rounds the bottom corners of the trench using a second etching environment. In this embodiment, the second etching environment is comprised of sulfur hexafluoride (SF6) and chlorine chemistry. In so doing, the present embodiment provides a method for forming a trench for a shallow trench isolation structure wherein the trench does not have sharp bottom corners formed therein.
In another embodiment of the present invention, the present invention performs a breakthrough etch to remove a native oxide layer disposed over a region of a semiconductor substrate. In so doing, a region of the semiconductor substrate is exposed. Next, the present embodiment etches a trench into the semiconductor substrate using an etching environment. The present embodiment also rounds the bottom corners of the trench using the same etching environment. In this embodiment, the etching environment is comprised of sulfur hexafluoride (SF6) and chlorine chemistry. In so doing, the present embodiment provides a method for forming a trench for a shallow trench isolation structure wherein the trench does not have sharp bottom corners formed therein.